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用vhdl语言编写的2进制到10进制转换的程序
- 本文为用vhdl语言编写的2进制到10进制转换的程序，为doc格式，使用前复制于maxplus等相应软件中使用。,This article was prepared by using VHDL language 2 hex to 10 hex conversion procedures for the doc format, the use of pre-replication in maxplus, such as the use of corresponding software.
jpeg.zip
- a jpeg compression core, a jpeg compression core
RGB2YCbCr.rar
- JPEG标准中图像彩色空间的转换，开发语言为Verilog,Standard JPEG image color space conversion, the development of language for Verilog
Chapter10
- 第十章的代码。 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相
JPEG
- 本文首先介绍了静态图像压缩（JPEG）编码算法的基本原理、压缩的实现过程及其重要过程的离散余弦变换（DCT）算法的实现原理及软件实现的例程，其次着重介绍了压缩过程中的DCT、量化和编码三个重要步骤的实现原理。-This paper describes the static image compression (JPEG) coding algorithm is the basic principle of compression process of the implementation pro
oc_mkjpeg
- Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.-Pure hardware JPEG Encoder design.
VERILOG-jpeg
- 用Verilog语言在FPGA上实现JPEG图片的解码，附带testbench-With the Verilog language in the FPGA to achieve JPEG image decoding, with testbench
jpeg
- 这是一个JPEG的编解码的VHDL程序代码-This is a JPEG codec the VHDL code
JPEGactFPGA
- 利用FPGA实现JPEG算法的研究与实现，研究生的论文，很有参考价值-JPEG algorithm using FPGA realization of Research and Implementation of, post-graduate thesis, a good reference
jpeg
- JPEG(Joint Photographic Expert Group,联合摄影专家组)编码的数据执行解压缩的各项功能.JPEG的VHDL实现代码-JPEG (Joint Photographic Expert Group, Joint Photographic Experts Group) encoding of data to implement the various functions of decompression. JPEG realization of VHDL code
jpeg.tar
- This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288). Image resolution is no
jpeg.tar
- jpeg硬件压缩代码，对学习jpeg压缩的同学非常有用-hardware jpeg compression code, the Student Study jpeg compression is very useful
jpeg_latest.tar
- JPEG descr iption by vhdl
etd-0901103-165524
- jpeg 2000 modules with definate improved design ideas on the hardware platorm. especiallyy EBCOT and MQ coder.
jpeg.tar
- vhdl source for jpeg beginner
JPEG
- Here is a quite detailed low level design document for the Core: Low Level Design Document for JPEG Encoder
vhdl-JPEG-enc
- JPEG Encoder,Here is a quite detailed low level design document for the Core: Low Level Design Document
fpga-jpeg
- 基于FPGA的JPEG图像压缩，实现JPEG图像的实时压缩-FPGA JPEG compress
FPGA_image
- fpga实现图像处理，JPEG标准下图象压缩，VHDL语言编程。-fpga implementation image processing, JPEG image compression under the standard, VHDL language programming.
JPEG-LS
- 基于改进JPEG-LS算法的遥感图像近无损压缩专利，由航天五院508所申报，很详细的介绍了算法和fpga的实现-Improved JPEG-LS algorithm near lossless compression patent, the space the five branches of 508 reporting, a detailed explanation of the algorithm and implementation fpga